module REG_EX_MEM (
    input clk,
    input rst_n,
    
    input [2:0] wd_sel_in,
    input rf_we_in,
    input dram_we_in,
    input [4:0] wR_in,
    input [31:0] wD_in,
    input [31:0] aluc_in,
    input [31:0] rD2_in,
    input [3:0] load_sel_in,
    input [2:0] store_sel_in,
    input [1:0] offset_in,

    output reg [3:0] load_sel_out,
    output reg [2:0] store_sel_out,
    
    output reg [2:0] wd_sel_out,
    output reg rf_we_out,
    output reg dram_we_out,
    output reg [4:0] wR_out,
    output reg [31:0] wD_out,
    output reg [31:0] aluc_out,
    output reg [31:0] rD2_out,
    output reg [1:0]  offset_out,

    input      [31:0] pc_in,
    output reg [31:0] pc_out,
    input             debug_have_inst_in,
    output reg        debug_have_inst_out
    );

    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      load_sel_out <=  3'b0;
        else            load_sel_out <= load_sel_in;
    end

    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      store_sel_out <=  2'b0;
        else            store_sel_out <= store_sel_in;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)  pc_out <= 32'b0;
        else        pc_out <= pc_in;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)  debug_have_inst_out <= 1'b0;
        else        debug_have_inst_out <= debug_have_inst_in;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      wd_sel_out <= 2'b0;
        else            wd_sel_out <= wd_sel_in;
    end

    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      offset_out <= 2'b0;
        else            offset_out <= offset_in;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      rf_we_out <= 1'b0;
        else            rf_we_out <= rf_we_in;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      dram_we_out <= 1'b0;
        else            dram_we_out <= dram_we_in;
    end

    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      wR_out <= 5'b0;
        else            wR_out <= wR_in;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      wD_out <= 32'b0;
        else            wD_out <= wD_in;
    end

    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      aluc_out <= 32'b0;
        else            aluc_out <= aluc_in;
    end
    
    always @ (posedge clk or negedge rst_n) begin
        if(!rst_n)      rD2_out <= 32'b0;
        else            rD2_out <= rD2_in;
    end

endmodule
